Gate arrays (a type of ASIC) and Field Programmable Gate Arrays (FPGAs) are well known in the art. In general, a gate array is an integrated circuit that includes a plurality of predetermined transistor sizes determined by the manufacturer or vendor. Once the transistor size is set, a plurality of transistors are deposited, in layers, on a substrate to form a base or generic array. The manufacturer creates a library of logic cells by combining a plurality of transistors.
When a user identifies a specific need or functionality for a gate array, then the final layer(s) are deposited over the base array, customizing the gate array in accordance with the user's needs. The individual logic cells are connected together in such a way so as to achieve an output desired by the user. After the gate array is manufactured, its internal logic is set and cannot be altered.
Although the cost of the final customized layers are borne by the user, savings are realized since the manufacturing costs associated with producing the base array of transistors is spread over a large number of gate arrays.
Static Random Access Memory (SRAM) based Field Programmable Gate Arrays are integrated circuits that are electrically programmable by the user/customer. The configuration of the FPGA may be changed from time to time to provide different outputs from the same integrated circuit when the user applies external control signals and a data stream to the FPGA.
An FPGA includes a plurality of configurable elements (e.g., AND Gates, NOR Gates, XOR Gates, flip flops, inverters and RAM) which, when connected together, form more complex functions. Furthermore, each configurable element can be connected together to provide even more complex functions. A specific function to be carried out by the configurable element is determined directly by the control signals and the data stream applied to the FPGA and, ultimately, to the configurable elements within the FPGA. In a common operation, the control signals are generated, and the data stream is stored and transmitted by control logic external to the FPGA. An example of the external control logic for generating the control signals is a microprocessor, and for storing the data stream is an erasable programmable read only memory (EPROM) chip.
When a user designs a circuit and/or circuit board in response to a particular need, a prototype is developed that may include FPGAs in order to facilitate testing and troubleshooting of the circuit. The data stream, stored on an EPROM, can be easily changed by the user. When the FPGA receives the new data stream, the logic elements within each configurable element and the connections between the configurable elements are changed (i.e., they are configured in accordance with the new data stream). Therefore, the output signals from the FPGA, which are generated in response to specific input signals, are changed. Since the output signals of the FPGA change, there is a corresponding effect on the overall user's circuit board.
After the user has finalized the design of the circuit on the circuit board, the layout of the circuit board can be redesigned and the FPGAs replaced by less expensive gate arrays. Since gate arrays do not have configurable logic elements they do not need external control signals; therefore, certain external logic circuits (e.g., EPROMs) can be eliminated, and extensive redesign of the circuit and circuit board may be required. Even though costs are incurred in redesigning the circuit board, for high volume productions of circuit boards, it is cost-effective to replace the FPGAs with gate arrays.
Xilinx, Inc. has developed a capability entitled HardWire to provide a pin-for-pin replacement for the Xilinx family of FPGAs. HardWire devices are identical to their corresponding FPGAs, however the programmable or configurable elements in the FPGA are removed and replaced with fixed metal connections (i.e., they are "hard-wired" together). The HardWire configuration circuitry is mapped directly from the Xilinx FPGA configuration circuitry. Since a HardWire device is architecturally identical to its corresponding FPGA, it has the same number of gates as the corresponding FPGA. Therefore, a reduction in manufacturing costs may be realized, but there is usually no increase in the area efficiency.